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Compilation and Architecture support to mitigate fault and side-channel attacks to modern microprocessors (2016 - present)
The project aims to leverage the synergy between high-performance architectures, parallelizing compilers, and computer security to provide hardware software co-design directions and automation in the deployment of mitigation against fault and side-channel attacks. The rationale behind this project is that existing, sound techniques from the high-performance computing domain can be re-purposed/architected under the light of rational threat models. The advantage of doing so, beyond leveraging a substantial body of literature, is to single setup mitigations against multiple threats, to promote sound composability of security properties and attack mitigation, as well as, to loosen the trade-off between performance and security mitigation. Notable examples are the use of vectorization for introducing resistance against DPA and fault-attacks to modern microprocessors, and the use of value prediction to mitigate fault attacks.
Qualcomm Technologies Inc kindly supported the project. 

 
Domain Specific Programmable Architecture for Lattice-based Cryptography Schemes (2016 - present)
The project aims to provides analysis, hardware co-design and hints to the semiconductor industry for early adoption of post-quantum cryptography schemes in hardware. Our study includes both compiler and micro-architectural optimization aspects. The specific focus of the project is on lattice-based cryptography, is because these schemes provide foundational security properties, ease of implementation and find applications to both traditional and emerging security
problems such as encryption (asymmetric, but also symmetric), digital signature, key exchange, homomorphic encryption, etc.
Lattice-based schemes require significant computational resources, making their realization in varying scenarios (e.g., from high-performance servers to resource-constrained IoT) challenging. Furthermore,
since these schemes are yet to be standardized, there is a critical need for rapid deployment in the face of emerging and changing standards. The project tackles both these issues (computational pressure and rapid deployment) by deploying programmable accelerators with specialized datapath and controllers that can achieve improved performance and energy efficiency. 
We developed a design flow, and with it, we developed a multitude of domain-specific processors to accommodate the largest pool of lattice-based cryptography schemes, including NewHope, Dilithium, Kyber, etc.  
Qualcomm Technologies Inc kindly supported the project. 


Feature-agnostic learning of computing system performance optimizations (2014 - present)
This project aims to introduce methodologies for program characterization and its application to computing performance problems (e.g., hardware procurement, performance modeling/ prediction, automatic performance test generation, compiler, and run-time optimization tuning) that abstract from the traditional feature engineering approach widely used in machine learning aided compilation/run-time. 
To this end, the project leverages datasets performance measurements to identify algorithmic and system level optimization solutions that can maximize application performance and uses modern machine learning recommender systems to finding optimized solutions - via low-rank matrix factorization.
Qualcomm Technologies Inc kindly supported the project. 


Corner cases software optimization in the polyhedral model (2015 - 2018)
This project aims to apply polyhedral optimization to the case of fused layers in artificial neural networks, for different target architectures. It does study the problem of polyhedral optimization for the targeted workloads at different levels of abstractions, including source-to-source and IR-to-IR. 

  

WebRTCBench (2012 - 2013)
This project provided a benchmark for Web Real-Time Communication, to profile the critical portion of the software architecture and give hints to its mapping on modern micro-architectures. The project was Kindly funded by Intel Corporation.
The benchmark is available at the following link: https://github.com/ucisysarch/WebRTCBench.