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Senior Member IEEE (Computer Society, Communication Society)

Member ACM (SIGARCH, SIGMICRO)

Guest Editor
  • IJPP S.I. Side-Channel and Fault Analysis of High-Performance Computing Platforms. Springer 2018 (to appear)

Editorial Board Member
  • Springer International Journal of Parallel Programming (IJPP).

Associate Editor
  • Springer Journal of Hardware and System Security (HaSS).

Technical Program Committee Member
  • Top Picks In Hardware Embedded Security (TopinHES) 2018
  • International Symposium on Hardware Oriented Security and Trust (HOST).
  • International Conference On Computer Aided Design (ICCAD).
  • Design Automation Conference (DAC), SEC2: Embedded and Cross-Layer Security. 
  • International Workshop on Fault Tolerance and Diagnosis in Cryptography (FDTC).
  • International Conference on Supercomputing (ICS).
  • Workshop on Physical Attacks and Inspection on Electronics (PAINE).

Organizer/Steering Committee Member
  • TAME: Forum on Trusted and Assured MicroElectronics (TAME).
  • NSF FOSTER: Workshop on FOundations of Secure and TrustEd  HardwaRe (FOSTER).

PANELS
  • TAME: Forum on Trusted and Assured MicroElectronics (TAME) 2018: "10 Years of Hardware Security Research: Is It All Hype or Steady Progress?"
  • NSF workshop on Side and Covert channels in Computing Systems (SCCS) 2018: "New Computing Paradigms to Mitigate Information Leakage."
  • TAME: Forum on Trusted and Assured MicroElectronics (TAME) 2017: "Need for National Technology Roadmap for Trusted and Assured Microelectronics."

Invited Talks
  • “Machine Learning IP Protection.” ICCAD, San Diego, Nov. ‘18
  • “Information Leakage and Mitigations - from smart cards to SoC.” Military and Aerospace Programmable Logic Devices (MAPLD), San Diego, May ‘18
  • “A Path Toward Early Adoption of Lattice-Based Cryptography Schemes in Hardware.” IEEE VLSI Test Symposium (VTS), San Francisco, Apr ‘18
  • “New Computing Paradigms to Mitigate Information Leakage.” NSF Workshop on Side and Covert Channels in Computing Systems, Washington DC, Mar’18  
  • “Who needs of Side-channel Mitigations? The Lessons Learned.” Electrical And Computer Engineering Department, UT Dallas, Jun 2017
  • “Side-channel attacks for modern targets: from smart-cards to complex embedded systems.” Electrical And Computer Engineering Department, UC San Diego, Apr 2017
  • “Side-channel attacks for modern targets.” Annual Conference on Cybersecurity at the Florida Institute for Cybersecurity (FICS) Research, University of Florida, Mar 2017
  • “Automatic construction of program optimization strategies.” AI/ML Seminar Series of the Center for Machine Learning and Intelligent Systems, University of California, Irvine Feb 2014

Conference and Workshop Talks
  • “Optimizing Program Performance via Similarity, Using a new Feature-agnostic Characterization Approach.” International Conference of Advanced Parallel Programming Technologies, Stockholm, Sweden, August 2013
  • “On the Determination of Inlining Vectors for Program Optimization.” International Conference on Compiler Construction, Rome, Italy, March 2013
  • “Just in time load balancing.” International Workshop on Languages and Compilers for Parallel Programming, Tokyo, Japan September 2012
  • “Selective Search of Inlining Vectors for Program Optimization.” ACM International Conference on Computing Frontiers, Cagliari, Italy, May 2012
  • “Performance Modeling for System Selection.” International Workshop on Compilers for Parallel Computing, Padova, Italy, January 2012
  • “Pruning Hardware Evaluation Space via Correlation-Driven Application Similarity Analysis.” at ACM International Conference on Computing Frontiers, Ischia, Italy, May 2011